The present invention relates to a ferroelectric-type nonvolatile semiconductor memory (so-called FERAM) and an operation method thereof.
In recent years, studies are actively made with regard to a ferroelectric-type nonvolatile semiconductor memory having a large capacity. A ferroelectric-type nonvolatile semiconductor memory (to be sometimes abbreviated as xe2x80x9cnonvolatile memoryxe2x80x9d hereinafter) permits rapid access and is nonvolatile, and it consumes less electric power and has strength against an impact, so that it is expected to be used as a main storage device in various electronic machines and equipment having functions of file storage and resume, such as a portable computer, a cellular phone and a game machine, or as a recording medium for recording voices or images.
The above nonvolatile memory is a fast rewritable nonvolatile memory according to a method in which a change in an accumulated charge amount in a capacitor member having a ferroelectric layer is detected by utilizing a fast polarization inversion and its residual polarization of the ferroelectric layer, and the nonvolatile memory comprises the capacitor member (memory cell) and a transistor for selection (transistor for switching). The capacitor member comprises, for example, a lower electrode, an upper electrode and the ferroelectric layer having a high dielectric constant xcex5 interposed between these electrodes. Data is written into and read out from the above nonvolatile memory by using the P-E hysteresis loop of the ferroelectric layer shown in FIG. 53. That is, when an external electric field is applied to the ferroelectric layer and then removed, the ferroelectric layer exhibits a spontaneous polarization. When an external electric field in the plus direction is applied, the residual polarization of the ferroelectric layer comes to be +Pr, and when an external electric field in the minus direction is applied, it comes to be xe2x88x92Pr. When the residual polarization is in the state of +Pr (see xe2x80x9cDxe2x80x9d in FIG. 53), such a state represents xe2x80x9c0xe2x80x9d, and when the residual polarization is in the state of xe2x88x92Pr (see xe2x80x9cAxe2x80x9d in FIG. 53), such a state represents xe2x80x9c1xe2x80x9d.
For discriminating the state of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, an external electric field, for example, in the plus direction is applied to the ferroelectric layer, whereby the polarization of the ferroelectric layer comes into the state of xe2x80x9cCxe2x80x9d in FIG. 53. In this case, when the data is xe2x80x9c0xe2x80x9d, the polarization state of the ferroelectric layer changes from the state of xe2x80x9cDxe2x80x9d to the state of xe2x80x9cCxe2x80x9d. When the data is xe2x80x9c1xe2x80x9d, the polarization state of the ferroelectric layer changes from the state of xe2x80x9cAxe2x80x9d to the state of xe2x80x9cCxe2x80x9d through the state of xe2x80x9cBxe2x80x9d. When the data is xe2x80x9c0xe2x80x9d, the polarization inversion does not take place in the ferroelectric layer. When the date is xe2x80x9c1xe2x80x9d, the polarization inversion takes place in the ferroelectric layer. As a result, there is caused a difference in the accumulated charge amount in the capacitor member. The above accumulated charge is detected as a signal current by bringing, into an ON-state, the transistor for selection in a selected nonvolatile memory. When the external electric field is brought into 0 after data is read out, the polarization state of the ferroelectric layer comes into the state of xe2x80x9cDxe2x80x9d in FIG. 53 both when the data is xe2x80x9c0xe2x80x9d and when it is xe2x80x9c1xe2x80x9d. That is, when the data is read out, the data xe2x80x9c1xe2x80x9d is once destroyed. When the data is xe2x80x9c1xe2x80x9d, therefore, the polarization is brought into the state of xe2x80x9cAxe2x80x9d through xe2x80x9cDxe2x80x9d and xe2x80x9cExe2x80x9d by applying the external electric field in the minus direction, to re-write data xe2x80x9c1xe2x80x9d.
The structure and the operation of a currently mainstream nonvolatile memory are proposed by S. Sheffiled et al. in U.S. Pat. No. 4,873,664. The above nonvolatile memory comprises two nonvolatile memory cells as shown in a circuit diagram of FIG. 54. In FIG. 54, each nonvolatile memory is surrounded by a dotted line. Each nonvolatile memory comprises, for example, transistors for selection TR11, and TR12 and capacitor members (memory cells) FC11 and FC12.
Concerning two-digit or three-digit subscripts, for example, a subscript xe2x80x9c11xe2x80x9d is a subscript that should be shown as xe2x80x9c1,1xe2x80x9d, and for example, a subscript xe2x80x9c111xe2x80x9d is a subscript that should be shown as xe2x80x9c1,1,1xe2x80x9d. For simplified showing, the subscripts are shown as two-digit or three-digit subscripts. Further, a subscript. xe2x80x9cMxe2x80x9d is used to show, for example, a plurality of memory cells or plate lines in a block, and a subscript xe2x80x9cmxe2x80x9d is used to show an individual, for example, of a plurality of the memory cells or the plate lines. A subscript xe2x80x9cNxe2x80x9d is used to show, for example, transistors for selection or sub-memory units in a block, and a subscript xe2x80x9cnxe2x80x9d is used to show, for example, an individual of the transistors for selection or the sub-memory units.
A complementary data is written into the above nonvolatile memory (a pair of the memory cells), and the nonvolatile memory stores 1 bit. In FIG. 54, symbol xe2x80x9cWLxe2x80x9d stands for a word line, symbol xe2x80x9cBLxe2x80x9d stands for a bit line, and symbol xe2x80x9cPLxe2x80x9d stands for a plate line. When one nonvolatile memory is taken, the word line WL1 is connected to a word line decoder/driver WD. The bit lines BL1 and BL2 are connected to a sense amplifier SA. Further, the plate line PL1 is connected to a plate line decoder/driver PD.
When the stored data is read out from the thus-structured nonvolatile memory, the word line WL1 is selected, and further, the plate line PL1 is driven. In this case, a complementary data appears between a pair of the bit lines BL1 and BL2 as voltages (bit line voltages) from a pair of the capacitor members FC11 and FC12 through the transistors for selection TR11 and TR12. The voltages (bit line voltages) between a pair of the bit lines BL1 and BL2 are detected with the sense amplifier SA.
One nonvolatile memory occupies a region surrounded by the word line WL1 and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, the smallest area of one nonvolatile memory is 8F2 when the minimum fabrication dimension is xe2x80x9cFxe2x80x9d. Therefore, the thus-structured nonvolatile memory has a smallest area of 8F2.
When it is attempted to increase the capacity of the above-structured nonvolatile memories, its realization can only rely on minuteness of fabrication dimension. Constitution of one nonvolatile memory requires two transistors for selection and two capacitor members. Further, it is required to arrange the plate lines at the same pitch as that at which the word lines are arranged. It is therefore almost impossible to arrange the nonvolatile memories at the minimum pitch, and in reality, the area that one nonvolatile memory occupies comes to be much greater than 8F2.
Moreover, it is also required to arrange the word line decoders/drivers WD and the plate line decoders/drivers PD at a pitch equal to a pitch at which the nonvolatile memories are arranged. In other words, two decoders/drivers are required for selecting one low-address. It is therefore difficult to layout peripheral circuits, and the area that the peripheral circuits occupy comes to be large.
One means for decreasing an area of a nonvolatile memory is disclosed in JP-A-121032/1997. As FIG. 55 shows a circuit diagram, the nonvolatile memory disclosed in the above Laid-open comprises a plurality of memory cells MC1M (for example, M=4) one end of each of which is connected to one end of one transistor for selection TR1 in parallel, and a plurality of memory cells MC2M one end of each of which is connected to one end of one transistor for selection TR2 in parallel. The memory cells MC1M pair with the memory cells MC2M. The other ends of the transistors for selection TR1 and TR2 are connected to the bit lines BL1 and BL2, respectively. The paired bit lines BL1 and BL2 are connected to a sense amplifier SA. Further, the other ends of the memory cells MC1m and MC2m (m=1, 2 . . . M) are connected to the plate line PLm, and the plate line PLm is connected to a plate line decoder/driver PD. Further, the word line WL is connected to a word line decoder/driver WD.
Complementary data is stored in a pair of the memory cells MC1m and MC2m (m=1, 2 . . . M). For reading out the data stored, for example, in the memory cells MC1k and MC2k (wherein k is one of 1, 2, 3 and 4), the word line WL is selected, and the plate line PLk is driven in a state where a voltage of (xc2xd)VCC is applied to the plate lines PLm (mxe2x89xa0k). The above VCC is, for example, a power source voltage. By the above procedure, the complementary data appears between a pair of the bit lines BL1 and BL2 as voltages (bit line voltages) from a pair of the memory cells MC1k and MC2k through the transistors for selection TR1 and TR2. And, the sense amplifier SA detects the voltages (bit line voltages) between a pair of the bit lines BL1 and BL2.
A pair of the transistors for selection TR1 and TR2 in the nonvolatile memory occupy a region surrounded by the word lines WL and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, a pair of the transistors for selection TR1 and TR2 in the nonvolatile memory have a minimum area of 8F2. Since, however, a pair of the transistors for selection TR1 and TR2 are shared by M sets of pairs of the memory cells MC1m and MC2m (m=1, 2 . . . M), the number of the transistors for selection TR1 and TR2 per bit can be decreased, and the layout of the word lines WL is moderate, so that the nonvolatile memory can be easily decreased in size. Further, with regard to the peripheral circuits, M bits can be selected with one word line decoder/driver WD and M plate line decoders/drivers PD. When the above constitution is employed, therefore, the layout in which the cell area is close to 8F2 can be attained, and a chip size equal to a DRAM can be attained.
When attempts are made to increase the capacity of a nonvolatile memory having a conventional structure, the capacity thereof is defined by the minimum fabrication dimension. As is clear in the above conventional example, the minimum cell area thereof is 8F2. This critical value is also true of DRAM. When every semiconductor memory such as EPROM is taken into account, the limit of area of a memory cell arranged in a region occupied by one bit line and one word line which lines are arranged at a minimum pitch is said to be 4F2.
However, the above minimum fabrication dimension, i.e., a decrease in a design rule can be attained only after micro-fabrication techniques including lithography as a main technique develop in the future. Further, such micro-fabrication techniques are facing increasing difficulties generation after generation, and the amount of investments comes to be huge amounts of money, which results in an increase in a chip cost. In the semiconductor memory, therefore, it is difficult to achieve break-through improvements in storage capacity at present for a short period of time.
The essential reason why the upper limit of the integration of a semiconductor memory is defined as described above involves the following two points.
First, a memory cell in a semiconductor memory is two-dimensionally arranged on a surface of a semiconductor substrate, and is not three-dimensionally stacked in any case. That is because almost all of conventional semiconductor memories include at least one transistor (FET) per storage unit. Since the transistors can be formed only in a good semiconductor substrate, it is no choice but to arrange the memory cell on the semiconductor substrate two-dimensionally. At present attempts are made to stack a semiconductor crystal layer by crystallization based on an epitaxial growth technique or a laser anneal technique. However, no sufficient yield or performances have been attained. Further, even if the above attempts can be successfully made, the number of steps increases approximately twice for manufacturing memory cell in the semiconductor crystal layer, which results in spoiling of a cost merit.
Second, accessing to a semiconductor memory is performed through a two-dimensional matrix made of word lines (row direction) and bit-lines (column direction). In a conventional semiconductor memory, a selection in the row direction is one-dimensionally performed through the word line, and a column selection is carried out from data set read out in the bit lines. In the conventional examples shown in FIGS. 54 and 55, a selection in the row direction is performed through the plate line, and yet, there is no difference in that the selection is performed substantially one-dimensionally.
If the integration degree of semiconductor memories should be doubled while keeping the page length as it is, it is naturally required to double the numbers of the word lines and plate lines. It is accordingly required to double the integration degree of the peripheral circuits for decoding and driving the word lines and the plate lines as well. These circuits naturally require transistors, so that they are two-dimensionally arranged near the cell array. There is therefore caused another difficulty in the layout of the peripheral circuits.
As described above, the memory cells per se are limited to the two-dimensional layout, and further, even if the memory cells are decreased in size, the address selection method that can be employed at present causes a difficulty on the layout of the peripheral circuits. The increase in the capacity of the semiconductor memory can be dependent only upon the development of a design rule.
Further, while the method of decreasing the area of the nonvolatile memory disclosed in JP-A-121032/1997 is very effective, it has the following problems.
That is, for example, when data xe2x80x9c1xe2x80x9d is written into the memory cell MC11 in a pair of the memory cells MC11 and MC21, the plate line PL1 is brought into a ground level (0 volt) and the bit line BL1 is brought to VCC, to polarize the ferroelectric layer. In this case, for retaining data xe2x80x9c0xe2x80x9d in the memory cell MC21, it is required to bring the bit line BL2 to a ground level (0 volt).
On the other hand, for preventing the destruction of the data stored in the memory cells MC1m and MC2m (m=2, 3, 4) connected to the non-selected plate lines PLm (m=2, 3, 4), the non-selected plate lines PLm (m=2, 3, 4) is fixed at (xc2xd)VCC that is an intermediate voltage between the voltages of the bit lines BL1 and BL2, to ease an electric field to be applied to the ferroelectric layer constituting the capacitor member of the non-selected memory cells MC1m and MC2m. That is, a disturbance of (xc2xd)VCC is exerted on the non-selected memory cells MC1m and MC2m.
Meanwhile, as an essential physical property, the ferroelectric material for constituting the ferroelectric layer has a temperature characteristic that its inversion voltage is negative. FIGS. 56A and 56B show P-E hysteresis loops of a ferroelectric material at 20xc2x0 C. and 105xc2x0 C. In FIGS. 56A and 56B, solid-line P-E hysteresis loops show a case where VCC=1.5 volts, and dotted-line P-E hysteresis loops show a case where VCC=1.0 volts. In these loops, a polarization difference between the state of data xe2x80x9c1xe2x80x9d and the state of data xe2x80x9c0xe2x80x9d at 0 volt is 2Pr, and the value of 2Pr corresponds to a signal amount (signal charge). In FIG. 56A, the inversion voltage at an operation temperature of 20xc2x0 C. is approximately xc2x10.9 volt. Therefore, if the nonvolatile memory is operated at VCC=1.5 volts, a signal charge of 7.9 xcexcC/cm2 can be retained at a disturbance voltage of (xc2xd)VCC without destroying data stored in the non-selected memory call. In contrast, the inversion voltage at 105xc2x0 C. is approximately xc2x10.55 volt. Therefore, if the nonvolatile memory is operated at VCC=1.5 volts, while a signal charge of 11 xcexcC/cm2 can be retained, the charge of the non-selected memory cell is inversed at the disturbance voltage of (xc2xd)VCC and the stored data is destroyed.
For preventing the inversion of the charge of the non-selected memory cell at an operation temperature of 105xc2x0 C. unlike the above, VCC is required to be approximately 1 volt. In this case, a signal charge of 6.9 xcexcC/cm2 can be retained. However, only a signal charge of 2.8 xcexcC/cm2 can be retained at 20xc2x0 C., and the signal amount decreases to excess.
As described above, the coercive voltage of the nonvolatile memory has a great negative temperature dependency. That is, with an increase in temperature, the coercive voltage of the nonvolatile memory decreases, and the charge of the non-selected capacitor member is liable to be inverted. Therefore, if no measures are taken against the characteristic that the inversion voltage of a ferroelectric material for constituting the ferroelectric layer has the above negative temperature characteristic, the operation of the nonvolatile memory in a temperature range required of LSI may be no longer ensured.
Further, when the nonvolatile memory having the above structure is more shrunk, it is inevitably required to decrease the area of the capacitor member. Further, data is stored on the basis of polarization in the ferroelectric layer, so that the amount of charge to be accumulated in the ferroelectric layer does not increase even if the thickness of the ferroelectric layer is decreased unlike the insulating layer in the DRAM, and the accumulated charge amount decreases in proportion to the area of capacitor member.
For attaining a nonvolatile memory of 256M bits, the capacitor member is required to have an area of approximately 0.1 xcexcm2. In this case, the accumulated charge amount comes to be approximately 10 fC, and when the bit line capacity is assumed to be 200 fF, a sense signal amount (potential that appears in a bit line during a reading operation) of only approximately 50 mV can be obtained. Such a sense signal amount provides an insufficient sense margin, and when the nonvolatile memory is further shrunk, readout of data stored in the nonvolatile memory can be no longer performed.
As one of measures to be taken against a decrease in the sense signal amount in DRAM, there is disclosed an amplification type memory cell called xe2x80x9cgain cellxe2x80x9d (for example, see JP-A-67861/1987 and JP-A-255269/1989). The gain cell whose circuit diagram is shown in FIG. 57A comprises a transistor for writing-in TRW, a transistor for read-out TRR, a transistor for detection TRS and a capacitor member C. When data is written into the gain cell, the transistor for writing-in TRW is brought into an ON-state to accumulate a charge in the capacitor member C. When data is read out from the gain cell, the transistor for read-out TRR is brought into an ON-state. The transistor for detection TRS comes into an ON-state or an OFF-state depending upon the data stored in the capacitor member C.
FIG. 57B shows a circuit diagram prepared when the above-constituted gain cell is applied to the conventional nonvolatile memory disclosed in U.S. Pat. No. 4,873,664. The above gain cell type nonvolatile memory can comprise a transistor for writing-in TRW, a transistor for read-out TRR, a transistor for detection TRS and a capacitor member FC. One source/drain region of the transistor for writing-in TRW is connected to the bit line BL, and the other source/drain region is connected to a lower electrode of the capacitor member FC. One end of the transistor for detection TRS is connected to a wiring having a predetermined potential VCC (for example, a power source line made of an impurity layer) and the other end thereof is connected to the bit line BL through the transistor for read-out TRR. Further, the lower electrode of the capacitor member FC is connected to the gate electrode of the transistor for detection TRS.
In the thus-constituted nonvolatile memory, pulse voltage is applied to the plate line PL when data is read out, and the operation state of the transistor for detection TRS constituted of a depression type NMOS-FET is controlled depending upon the amount of an accumulated charge caused on the basis of whether or not polarization inversion takes place in the capacitor member FC. That is, when the transistor for read-out TRR is brought into an ON-state after the bit line BL is equalized to 0 volt, a current flows from the power source VCC through the transistor for detection TRS and the transistor for read-out TRR, and a potential appears in the bit line BL. Such a potential is dependent upon the data stored in the nonvolatile memory cell. Due to this, it can be known whether the data stored in the capacitor member FC is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. That is, on the basis of a small accumulated charge in the capacitor member FC, a great bit line load can be driven.
However, the above-constituted nonvolatile memory has a problem that three transistors are required per memory cell, so that the cell area per bit greatly increases, and that the cost per bit increases.
When the data is read out and when the pulse voltage is applied to the plate line PL, polarization inversion takes place only when a sufficient potential difference is caused between the upper electrode connected to the plate line PL and the lower electrode connected to the gate electrode of the transistor for detection TRS. When the data is read out, however, the lower electrode connected to the gate electrode of the transistor for detection TRS is in a floating state, and the load capacity thereof is only equal approximately to the gate capacity of the transistor for detection TRS. When the pulse voltage is applied to the plate line PL, therefore, the potential of the lower electrode greatly increases according to the coupling of the upper electrode and the lower electrode. As a result, no sufficient electric field is formed between the upper electrode and the lower electrode, which causes a problem that no polarization inversion takes place in the ferroelectric layer. For preventing the above potential increase caused on the lower electrode by the coupling, it is required to add a load capacity several times larger than that of the capacity member FC to the lower electrode, and for this purpose, an additional capacitor is required. However, the cell area is greatly increased accordingly.
It is a first object of the present invention to provide a ferroelectric-type nonvolatile semiconductor memory that can be increased in capacity without being limited by the minimum fabrication dimension and is more highly integrated.
It is a second object of the present invention to provide a ferroelectric-type nonvolatile semiconductor memory that permits a decrease in the size of peripheral circuits by decreasing the number of driving lines for address selection.
Further, it is a third object of the present invention to provide a ferroelectric-type nonvolatile semiconductor memory that compatibly allows a decrease in the size of memory cells and a decrease in the number of peripheral circuits and permits an increase in consistent integration degree as an entire device.
Further, it is a fourth object of the present invention to provide a ferroelectric-type nonvolatile semiconductor memory that is provided with measures against a characteristic that the inversion voltage of a ferroelectric material for constituting a ferroelectric layer has a negative temperature characteristic, i.e., the negative temperature dependency of coercive voltage of the ferroelectric-type nonvolatile semiconductor memory, and which can reliably ensure operation in a required temperature range.
Further, it is a fifth object of the present invention to provide a gain cell type ferroelectric-type nonvolatile semiconductor memory that permits a decrease in area per bit and allows reliable readout of stored data, that is, which makes it possible to obtain a sufficient sense signal amount.
Further, it is a sixth object of the present invention to provide a ferroelectric-type nonvolatile semiconductor memory which is more highly integrated and is excellent in resistance to disturbance, and which permits fast operation and a low consumption power, and an operation method thereof.
A ferroelectric-type nonvolatile semiconductor memory according to a first aspect of the present invention for achieving the above first to third objects comprises;
(A) a bit line,
(B) a transistor for selection,
(C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein Nxe2x89xa72 and Mxe2x89xa72, and
(D) plate lines in the number of Mxc3x97N,
in which
the memory units in the number of N are stacked through an insulating interlayer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes are in common in each memory unit, and the common first electrode is connected to the bit line through the transistor for selection, and
the second electrode of the m-th memory cell in the n-th memory unit is connected to the [(nxe2x88x921)M+m]-th plate line wherein m=1, 2 . . . M and n=1, 2 . . . N.
A ferroelectric-type nonvolatile semiconductor memory according to a second aspect of the present invention for achieving the above first to third objects differs from the ferroelectric-type nonvolatile semiconductor memory according to the first aspect of the present invention in constitution of the transistor for selection and constitution of the plate lines. That is, the ferroelectric-type nonvolatile semiconductor memory according to the second aspect of the present invention comprises;
(A) a bit line,
(B) transistors for selection in the number of N wherein Nxe2x89xa72,
(C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein Mxe2x89xa72, and
(D) plate lines in the number of M,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes are in common in each memory unit,
the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M.
In a preferred embodiment of the ferroelectric-type nonvolatile semiconductor memory according to the second aspect of the present invention, the memory units in the number of N are stacked through an insulating interlayer.
A ferroelectric-type nonvolatile semiconductor memory according to a third aspect of the present invention for achieving the above first to third objects of the present invention differs from the ferroelectric-type nonvolatile semiconductor memory according to the second aspect of the present invention in constitution of the second electrode. That is, the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention comprises;
(A) a bit line,
(B) transistors for selection in the number of 2N wherein Nxe2x89xa71,
(C) memory units in the number of 2N, each memory unit comprising memory cells in the number of M wherein Mxe2x89xa72, and
(D) plate lines in the number of M,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes are in common in each memory unit,
the common first electrode in the (2nxe2x88x921)-th memory unit is connected to the bit line through the (2nxe2x88x921)-th transistor for selection wherein n=1, 2 . . . N,
the common first electrode in the 2n-th memory unit is connected to the bit line through the 2n-th transistor for selection, and
the m-th memory cell constituting the (2nxe2x88x921)-th memory unit and the m-th memory cell constituting the 2n-th memory unit share the second electrode, and the shared m-th second electrode is connected to the m-th plate line wherein m=1, 2 . . . M.
A ferroelectric-type nonvolatile semiconductor memory according to a fourth aspect of the present invention for achieving the above first to third objects of the present invention comprises a first memory unit and a second memory unit,
the first memory unit comprising;
(A-1) a first bit line,
(B-1) first transistor or transistors for selection in the number of N wherein Nxe2x89xa71,
(C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein Mxe2x89xa72, and
(D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
the second memory unit comprising;
(A-2) a second bit line,
(B-2) second transistor or transistors for selection in the number of N,
(C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M, and
(D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
in which
the first sub-memory unit is stacked on the second sub-memory unit through an insulating interlayer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N; the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection; and the second electrode of the m-th-place first memory cell is connected to the common m-th plate line wherein m=1, 2 . . . M, and
in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are in common in the n-th-place second sub-memory unit; the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection; and the second electrode of the m-th-place second memory cell is connected to the common m-th plate line.
A ferroelectric-type nonvolatile semiconductor memory according to a fifth aspect of the present invention for achieving the above first to third objects differs from the ferroelectric-type nonvolatile semiconductor memory according to the fourth aspect of the present invention in constitution of the second electrode. That is, the ferroelectric-type nonvolatile semiconductor memory according to the fifth aspect of the present invention comprises a first memory unit and a second memory unit,
the first memory unit comprising;
(A-1) a first bit line,
(B-1) first transistor or transistors for selection in the number of N wherein Nxe2x89xa71,
(C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein Mxe2x89xa72, and
(D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
the second memory unit comprising;
(A-2) a second bit line,
(B-2) second transistor or transistors for selection in the number of N,
(C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M, and
(D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N; and the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection,
in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are in common in the n-th-place second sub-memory unit; and the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection, and
the m-th-place first memory cell constituting the n-th-place first sub-memory unit in the first memory unit and the m-th-place second memory cell constituting the n-th-place second sub-memory unit in the second memory unit share the second electrode, and the shared m-th second electrode is connected to the m-th plate line wherein m=1, 2 . . . M.
In the ferroelectric-type nonvolatile semiconductor memory according to the fourth or fifth aspect of the present invention, preferably, one of the first bit line and the second bit line is connected to a sense amplifier to which the other is connected. In this case, the n-th-place first transistor for selection and the n-th-place second transistor for selection may be connected to the same word line or different word lines. Depending upon an operation method of the ferroelectric-type nonvolatile semiconductor memory, 1 bit may be stored in one memory cell, or complementary data may be stored in a pair of the memory cells.
In the ferroelectric-type nonvolatile semiconductor memory according to the first or second aspect of the present invention, it is sufficient to satisfy Mxe2x89xa72, and for example, the practical value of M includes exponents of 2 (2, 4, 8 . . . ). Further, it is sufficient to satisfy Nxe2x89xa72, and for example, the practical value of N includes exponents of 2 (2, 4, 8 . . . ).
In the ferroelectric-type nonvolatile semiconductor memory according to any one of the third to fifth aspects of the present invention, it is sufficient to satisfy Mxe2x89xa72, and for example, the practical value of M includes exponents of 2 (2, 4, 8 . . . ). Further, it is sufficient to satisfy Nxe2x89xa71, and for example, the practical value of N includes 1 and exponents of 2 (2, 4, 8 . . . ).
The ferroelectric-type nonvolatile semiconductor memory according to any one of the first to fifth aspects of the present invention, a plurality of memory cells share one transistor for selection. Further, the memory unit or the sub-memory unit is allowed to have a three-dimensionally stacked structure, whereby there is no case limited by the number of transistors occupying the surface of a semiconductor substrate, the storage capacity can be remarkably increased as compared with any conventional ferroelectric-type nonvolatile semiconductor memory, and the effective occupation area per bit storage unit can be remarkably decreased.
In the ferroelectric-type nonvolatile semiconductor memory according to any one of the second to fifth aspects of the present invention, further, the address selection in the row direction is performed on the basis of a two-dimensional matrix constituted of the transistors for selection and the plate lines. For example, when a row address selection unit is constituted of 8 transistors for selection and 8 plate lines, for example, 64-bit memory cells can be selected with 16 decoder/driver circuits. The storage capacity can be quadrupled even if the ferroelectric-type nonvolatile semiconductor memory has an integration degree equal to a conventional one. Further, the number of peripheral circuits and driving wirings for address selection can be decreased.
In the ferroelectric-type nonvolatile semiconductor memory according to any one of the first to fifth aspects of the present invention, preferably, the memory unit or the sub-memory unit has a 2P-layered structure (p=1, 2, 3 . . . ) such as a two-layered, four-layered or eight-layered structure.
In a preferred embodiment of the ferroelectric-type nonvolatile semiconductor memory according to the first or second aspect of the present invention, preferably, the ferroelectric layer constituting the memory cells of the memory unit positioned above has a lower crystallization temperature than the ferroelectric layer constituting the memory cells of the memory unit positioned below. In the ferroelectric-type nonvolatile semiconductor memory according to the third aspect of the present invention, when Nxe2x89xa72, the ferroelectric layer constituting the memory cells of a set of the memory units positioned above has a lower crystallization temperature than the ferroelectric layer constituting the memory cells of a set of the memory units positioned below. In the ferroelectric-type nonvolatile semiconductor memory according to the fourth or fifth aspect of the present invention, preferably, the ferroelectric layer constituting the memory cells of the sub-memory unit positioned above has a lower crystallization temperature than the ferroelectric layer constituting the memory cells of the sub-memory unit positioned below.
The ferroelectric-type nonvolatile semiconductor memory according to a sixth aspect of the present invention for achieving the above first object is a ferroelectric-type nonvolatile semiconductor memory having memory cells each of which comprises a first electrode, a ferroelectric layer and a second electrode and which are stacked through an insulating interlayer, in which the ferroelectric layer constituting the memory cell positioned above has a lower crystallization temperature than the ferroelectric layer constituting the memory cell positioned below.
In the ferroelectric-type nonvolatile semiconductor memory according to the sixth aspect of the present invention, the memory cells can have a 2P-layered structure (p=1, 2, 3 . . . ) such as a two-layered, four-layered or eight-layered structure.
In the ferroelectric-type nonvolatile semiconductor memory according to the sixth aspect of the present invention or in a preferred embodiment of the ferroelectric-type nonvolatile semiconductor memory according to any one of the first to fifth aspects of the present invention, the crystallization temperature of the ferroelectric layer constituting the memory cell can be determined, for example, by means of an X-ray diffraction analyzer or a surface scanning electron microscope. Specifically, for example, a ferroelectric material layer is formed and then heat-treated for crystallization promotion by changing heat-treatment temperatures for crystallization of the ferroelectric material layer, the heat-treated ferroelectric material layer is subjected to X-ray diffraction analysis and a diffraction pattern intensity characteristic of the ferroelectric material (height of diffraction peak) is evaluated, whereby the crystallization temperature of the ferroelectric layer can be determined.
Meanwhile, for producing a ferroelectric-type nonvolatile semiconductor memory having a constitution in which capacitor members to be described later, the memory units or the sub-memory units are stacked, the heat treatment (that will be referred to as xe2x80x9ccrystallization heat treatmentxe2x80x9d) is carried out for crystallization of the ferroelectric layer or a ferroelectric thin film constituting the ferroelectric layer, and it is required to carry out the above crystallization heat treatment as many times as the number of stacked stages of the capacitor members, the memory units or the sub-memory units. The capacitor members, the memory unit(s) or the sub-memory unit(s) positioned on the lower stage(s) are subjected to the crystallization heat treatment for a longer period of time, and the capacitor members, the memory unit(s) or the sub-memory unit(s) positioned on the upper stage(s) are subjected to the crystallization heat treatment for a shorter period of time. When optimum crystallization heat treatment is carried out on the capacitor members, the memory unit(s) or the sub-memory unit(s) positioned on the upper stage(s), the capacitor members, the memory unit(s) or the sub-memory unit(s) positioned on the lower stage(s) may suffer a heat load to excess, and the capacitor members, the memory unit(s) or the sub-memory unit(s) positioned on the lower stage(s) may be deteriorated in properties. It is thinkable to employ a method in which the capacitor members, the memory units or the sub-memory units are formed in a multi-stage and subjected to the crystallization heat treatment once. However, the above method is liable to involve problems that the ferroelectric layers cause a great change in volume during the crystallization and that each ferroelectric layer highly possibly causes degassing so that the ferroelectric layers undergo cracking or peeling.
In the ferroelectric-type nonvolatile semiconductor memory according to the sixth aspect of the present invention or in a preferred embodiment of the ferroelectric-type nonvolatile semiconductor memory according to any one of the first to fifth aspects of the present invention, the ferroelectric layer constituting the capacitor members, the memory unit(s) or the sub-memory unit(s) positioned above has a lower crystallization temperature than the ferroelectric layer constituting the capacitor members, the memory unit(s) or the sub-memory unit(s) positioned below, so that there is caused no problem that the memory cells for constituting the capacitor members, the memory units or the sub-memory units are deteriorated in properties, even if the above crystallization heat treatment is carried out as many times as the number of stacked stages of the capacitor members, the memory units or the sub-memory units. Further, the memory cells for constituting the capacitor members, the memory units or the sub-memory units can be heat-treated for crystallization under optimum conditions, so that a ferroelectric-type nonvolatile semiconductor memory excellent in properties can be obtained.
The ferroelectric-type nonvolatile semiconductor memory according to a seventh aspect of the present invention for achieving the fourth object is a ferroelectric-type nonvolatile semiconductor memory having a memory unit in which a plurality of memory cells having a capacitor member having a ferroelectric layer are provided and which has a structure in which a disturbance takes place in non-selected memory cells when a selected memory cell is accessed,
in which provided is a power source circuit that is connected to the capacitor member and whose output has a negative temperature characteristic.
The ferroelectric-type nonvolatile semiconductor memory according to any one of the first to sixth aspect of the present invention, including the preferred embodiments thereof, can be applied to the ferroelectric-type nonvolatile semiconductor memory according to the seventh aspect of the present invention.
As described above, the ferroelectric-type nonvolatile semiconductor memory according to the seventh aspect of the present invention is provided with the power source circuit that is connected to the capacitor member and whose output has a negative temperature characteristic, so that the voltage outputted from the power source circuit decreases when the operation temperature increases and the coercive voltage decreases. As a result, the value of (xc2xd)VCC decreases, and the charge inversion of the capacitor member in the non-selected memory cell can be prevented. The above disturbance refers to a phenomenon that an electric field is exerted on the ferroelectric layer of the capacitor member in the non-selected memory cell in the direction in which the polarization is inverted, that is, in the direction in which the stored data is deteriorated or destroyed.
The ferroelectric-type nonvolatile semiconductor memory according to the seventh aspect of the present invention may have a constitution in which one end of the capacitor member is connected to a bit line, the other end thereof is connected to a plate line, and the power source circuit is connected to the bit line or the plate line or is connected to the bit line and the plate line.
In the ferroelectric-type nonvolatile semiconductor memory according to the seventh aspect of the present invention, preferably, the power source circuit comprises;
(a) a reference-voltage circuit,
(b) a comparator having a first input portion into which a reference voltage outputted from the reference-voltage circuit is inputted, and
(c) a circuit for applying a negative feed back to an output voltage from the comparator according to the output voltage from the comparator, for example, a PMOS-type FET having a gate portion to which the output voltage from the comparator is inputted and a drain region connected to a second input portion of the comparator and the capacitor member.
The power source circuit can be constituted of a reference-voltage circuit alone. The connection of the drain region of the PMOS type FET to the capacitor member specifically means it is connected to the bit line or the plate line or is connected to the bit line and the plate line.
For simplifying the circuit, preferably, the reference-voltage circuit comprises a first resistance element having one end connected to a power source and a second resistance element having one end connected to the other end of the first resistance element and the other end grounded, and has a constitution in which the reference voltage is outputted from a connection portion of the first resistance element and the second resistance element.
In this case, there may be employed a constitution in which the first resistance element and the second resistance element have a negative temperature characteristic (that is, the resistance value decreases with an increase in temperature) and the absolute value of a change in the resistance value of the second resistance element based on the temperature change is greater than the absolute value of a change in the resistance value of the first resistance element based on the temperature change. The above absolute value of a change in the resistance value based on the temperature change can be expressed by |r2xe2x88x92r1| wherein r1 is an electric resistance value at a temperature of t1xc2x0 C. and r2 is an electric resistance value at a temperature of t2xc2x0 C. (t2 greater than t1). Specifically, the first resistance element and the second resistance element can be constituted of a resistance material. More specifically, for example, there can be employed a constitution in which the first resistance element comprises a semiconductor layer doped with an impurity and the second resistance element comprises a semiconductor layer doped with an impurity having a concentration lower than the impurity concentration of the semiconductor layer constituting the first resistance element; or a constitution in which the first resistance element comprises an Sixe2x80x94Ge semiconductor layer and the second resistance element comprises an Si semiconductor layer. The first resistance element and the second resistance element shall not be limited to the above constitutions. Alternatively, there may be also employed a constitution in which the first resistance element and the second resistance element have a positive temperature characteristic (that is, the resistance value increases with an increase in temperature) and the absolute value of a change in the resistance value of the second resistance element based on the temperature change is smaller than the absolute value of a change in the resistance value of the first resistance element based on the temperature change.
Alternatively, the above case may employ a constitution in which the first resistance element comprises a resistance material, and the second resistance element comprises at least one PMOS FET having a drain portion and a gate portion which are short-circuited (a structure formed of PMOS FETs connected in series in some case).
Alternatively, the above case may employ a constitution in which the first resistance element has a positive temperature characteristic (that is, the resistance value increases with an increase in temperature), and the second resistance element has a negative temperature characteristic (that is, the resistance value decreases with an increase in temperature). Specifically, there may be employed a constitution in which the first resistance element comprises a PMOS FET having a gate portion grounded and the second resistance element comprises a resistance material, while the constitution shall not be limited the above.
The ferroelectric-type nonvolatile semiconductor memory according to an eighth aspect of the present invention for achieving the above fourth object is a ferroelectric-type nonvolatile semiconductor memory having a memory unit in which a plurality of memory cells having a capacitor member having a ferroelectric layer are provided and which has a structure in which a disturbance takes place in non-selected memory cells when a selected memory cell is accessed,
in which one end of the capacitor member is connected to a bit line and the other end thereof is connected to a plate line, and
provided is a clamp circuit which is connected to the bit line and whose clamp voltage has a negative temperature characteristic.
The ferroelectric-type nonvolatile semiconductor memory according to any one of the first to sixth aspects of the present invention, including preferred embodiments thereof, can be applied to the ferroelectric-type nonvolatile semiconductor memory according to the eighth aspect of the present invention. The ferroelectric-type nonvolatile semiconductor memory according to the seventh aspect of the present invention and the ferroelectric-type nonvolatile semiconductor memory according to the eighth aspect of the present invention may be combined.
In the ferroelectric-type nonvolatile semiconductor memory according to the eighth aspect of the present invention, the clamp circuit whose clamp voltage has a negative temperature characteristic (that is, the clamp voltage decreases or lowers with an increase in temperature) is connected to the bit line, so that the voltage (potential) of the bit line is clamped to a low voltage (potential) when the operation temperature increases and the coercive voltage decreases. As a result, the charge inversion of the non-selected capacitor member can be prevented.
The ferroelectric-type nonvolatile semiconductor memory according to the eighth aspect of the present invention may have a constitution in which a power source circuit connected to the plate line is further provided and the output of the power source circuit has a negative temperature characteristic. The power source circuit connected to the plate line can be structured to have the same constitution as that of the power source circuit connected to the plate line in the ferroelectric-type nonvolatile semiconductor memory according to the seventh aspect of the present invention.
In the ferroelectric-type nonvolatile semiconductor memory according to the eighth aspect of the present invention, desirably, the clamp circuit is constituted to have a structure in which PMOS FETs whose drain portion and gate portion are short-circuited each are connected in series, while the structure shall not be limited thereto.
The ferroelectric-type nonvolatile semiconductor memory according to a ninth aspect of the present invention for achieving the above fifth object is a ferroelectric-type nonvolatile semiconductor memory comprising;
(A) a bit line,
(B) a transistor for selection,
(C) a memory unit comprising memory cells in the number of M wherein Mxe2x89xa72, and
(D) plate lines in the number of M,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes of the memory cells are in common in each memory unit,
the common first electrode is connected to the bit line through the transistor for selection, and
the second electrode constituting the memory cell is connected to the plate line, and
further in which
(E) a signal detective circuit for detecting a change in potential of the common first electrode and transmitting a detection result to the bit line as a current or a voltage is further provided.
In the ferroelectric-type nonvolatile semiconductor memory according to the ninth aspect of the present invention, preferably, the transistor for selection and the signal detective circuit are formed on a semiconductor substrate, and the memory unit is formed on an insulation layer formed on the semiconductor substrate. The number of the memory unit may be 1 or at least 2. In the latter case, preferably, a plurality of the memory units are stacked through an insulating interlayer.
The ferroelectric-type nonvolatile semiconductor memory according to a tenth aspect of the present invention for achieving the above fifth object is a so-called gain cell type ferroelectric-type nonvolatile semiconductor memory and comprises;
(A) a bit line,
(B) a transistor for writing-in,
(C) a memory unit comprising memory cells in the number of M wherein Mxe2x89xa72, and
(D) plate lines in the number of M,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes of the memory cells are in common in each memory unit,
the common first electrode is connected to the bit line through the transistor for writing-in, and
the second electrode constituting the memory cell is connected to the plate line, and
the ferroelectric-type nonvolatile semiconductor memory further having;
(E) a transistor for detection, and
(F) a transistor for read-out,
and further in which one end of the transistor for detection is connected to a wiring having a predetermined potential, and the other end thereof is connected to the bit line through the transistor for read-out, and
when data stored in the memory cell is read out, the transistor for read-out is brought into a continuity state, and the operation of the transistor for detection is controlled by means of a potential that takes place in the common first electrode on the basis of the data stored in the memory cell.
The ferroelectric-type nonvolatile semiconductor memory according to an eleventh aspect of the present invention for achieving the fifth aspect is a so-called gain cell type ferroelectric-type nonvolatile semiconductor memory and comprises;
(A) a bit line,
(B) a transistor for writing-in,
(C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein Nxe2x89xa72 and Mxe2x89xa72,
(D) transistors for selection in the number of N, and
(E) plate lines in the number of M, each plate line being common to the memory cells each of which constitutes each of the memory units in the number of N,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes are in common in each memory unit,
the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection and the transistor for writing-in wherein n=1, 2 . . . N, and
the second electrode constituting the m-th memory cell is connected to the common m-th plate line wherein m=1, 2 . . . M,
the ferroelectric-type nonvolatile semiconductor memory further comprising;
(F) a transistor for detection, and
(G) a transistor for read-out,
and further in which one end of the transistor for detection is connected to a wiring having a predetermined potential, and the other end thereof is connected to the bit line through the transistor for read-out, and
when data stored in the memory cell constituting the n-th memory unit is read out, the n-th transistor for selection and the transistor for read-out are brought into a continuity state, and the operation of the transistor for detection is controlled by means of a potential that takes place in the common first electrode on the basis of the data stored in the memory cell.
In the ferroelectric-type nonvolatile semiconductor memory according to the eleventh aspect of the present invention, it is sufficient to satisfy Nxe2x89xa72, and the actual value of N includes, for example, exponents of 2 (2, 4, 8 . . . ).
In the ferroelectric-type nonvolatile semiconductor memory according to the ninth, tenth or eleventh aspect of the present invention, desirably, the value of M satisfies 2xe2x89xa6Mxe2x89xa7128, preferably 4xe2x89xa6Mxe2x89xa732.
In the ferroelectric-type nonvolatile semiconductor memory according to the tenth or eleventh aspect of the present invention, preferably, various transistors are formed on a silicon semiconductor substrate, an insulation layer is formed on the various transistors and the memory cells are formed on the insulation layer in view of decreasing the cell area. In some cases, a plurality of the memory units may be stacked through an insulating interlayer. The ferroelectric-type nonvolatile semiconductor memory according to any one of the first to sixth aspect of the present invention, including preferred embodiments thereof, may be applied to the ferroelectric-type nonvolatile semiconductor memory according to the tenth or eleventh aspect of the present invention, or further to the ferroelectric-type nonvolatile semiconductor memory according to the ninth aspect of the present invention having two or more memory units. Further, the ferroelectric-type nonvolatile semiconductor memory according to the ninth, tenth or eleventh aspect of the present invention and the ferroelectric-type nonvolatile semiconductor memory according to the seventh or eighth aspect of the present invention may be combined.
When the various transistors are constituted of FETs in the constitution of the ferroelectric-type nonvolatile semiconductor memory according to the tenth aspect of the present invention, specifically, there can be employed a constitution in which one source/drain region of the transistor for writing-in is connected to the bit line, the other source/drain region thereof is connected to the common first electrode, one source/drain region of the transistor for detection is connected to a wiring having a predetermined potential (for example, a power source line made of an impurity layer), the other source/drain region thereof is connected to one source/drain region of the transistor for read-out, the other source/drain region of the transistor for read-out is connected to the bit line, and further, the common first electrode (or the other source/drain region of the transistor for writing-in) is connected to the gate electrode of the transistor for detection. The constitution in which the other source/drain region of the transistor for detection is connected to one source/drain region of the transistor for read-out includes a constitution in which the other source/drain region of the transistor for detection and the one source/drain region of the transistor for read-out occupy one source/drain region.
When the various transistors are constituted of FETs in the constitution of the ferroelectric-type nonvolatile semiconductor memory according to the eleventh aspect of the present invention, specifically, there can be employed a constitution in which one source/drain region of the transistor for writing-in is connected to the bit line, the other source/drain region thereof is connected to one source/drain region of each of the transistors for selection in the number of N, the other source/drain region of the n-th transistor for selection is connected to the common first electrode constituting the n-th memory unit, one source/drain region of the transistor for detection is connected to a wiring having a predetermined potential, the other source/drain region thereof is connected to one source/drain region of the transistor for read-out, the other source/drain region of the transistor for read-out is connected to the bit line, and, the common first electrode constituting each memory unit (or the other source/drain region of the transistor for writing-in) is connected to the gate electrode of the transistor for detection. The constitution in which the other source/drain region of the transistor for detection is connected to one source/drain region of the transistor for read-out includes a constitution in which the other source/drain region of the transistor for detection and the one source/drain region of the transistor for read-out occupy one source/drain region.
In the ferroelectric-type nonvolatile semiconductor memory according to the ninth aspect of the present invention, since the memory cells in the number of M are provided for one transistor for selection and the signal detective circuit, the cell area per bit can be decreased. In the ferroelectric-type nonvolatile semiconductor memory according to the tenth aspect of the present invention, since the memory cells in the number of M are provided for one transistor for writing-in, one transistor for detection and one transistor for read-out, the cell area per bit can be decreased. In the ferroelectric-type nonvolatile semiconductor memory according to the -eleventh aspect of the present invention, since the memory cells in the number of Mxc3x97N are provided for one transistor for writing-in, one transistor for detection, one transistor for read-out and transistors for selection in the number of N, the cell area per bit can be further decreased. Further, a change in potential of the common first electrode is detected with the signal detective circuit, or the operation of the transistor for detection is controlled by means of a potential that takes place in the common first electrode on the basis of the data stored in the memory cell, and the first electrode is common to the memory cells in the number of M, so that there is caused a state in which a kind of additional load capacity is added to the first electrode. As a result, when a voltage is applied to the plate line for reading out the data, an increase in the potential of the first electrode can be suppressed, and a sufficient potential difference is caused between the first electrode and the second electrode, so that a reliable polarization inversion takes place in the ferroelectric layer.
The operation method of a ferroelectric-type nonvolatile semiconductor memory according to a first aspect of the present invention for achieving the above sixth object is an operation method of a ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit,
the first memory unit comprising;
(A-1) a first bit line,
(B-1) first transistor or transistors for selection in the number of N wherein Nxe2x89xa71,
(C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein Mxe2x89xa72, and
(D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
the second memory unit comprising;
(A-2) a second bit line,
(B-2) second transistor or transistors for selection in the number of N,
(C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M, and
(D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N; the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection; and the second electrode of the m-th-place first memory cell is connected to the common m-th-place plate line wherein m =1, 2 . . . M, and
in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are common in the n-th-place second sub-memory unit; the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection; and the second electrode of the m-th-place second memory cell is connected to the common m-th-place plate line,
the method comprising performing reading out data stored in the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line and re-writing data into the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line by performing potential rising (voltage rising) and potential falling (voltage falling) once each.
In the operation method of the ferroelectric-type nonvolatile semiconductor memory according to the first aspect of the present invention (to be abbreviated as xe2x80x9coperation method according to the first aspect of the present inventionxe2x80x9d hereinafter), there may be employed a constitution in which latch circuits in the number of 2N are provided between the first bit line and the second bit line for latching data stored in the first memory cells and the second memory cells, re-writing into the first memory cell constituting the n-th place first sub-memory unit is carried out according to the data latched in the (2nxe2x88x921)-th latch circuit, and re-writing into the second memory cell constituting the n-th second sub-memory unit is carried out according to the data latched in the 2n-th latch circuit. That is, 1 bit can be stored in each of the first memory cell constituting the n-th-place first sub-memory unit and the second memory cell constituting the n-th-place second sub-memory unit which memory cells share the plate line (i.e., form a pair), whereby the higher integration of the ferroelectric-type nonvolatile semiconductor memory can be attained. The thus-constituted operation method according to the first aspect of the present invention will be referred to as xe2x80x9coperation method according to the first constitution of the present inventionxe2x80x9d.
The operation method according to the first constitution of the present invention may employ a constitution in which, when the data stored in the first memory cell is read out, the first transistor for selection is brought into an ON-state, the second transistor for selection is brought into an OFF-state and a reference potential is applied to the second bit line, and when the data stored in the second memory cell is read out, the second transistor for selection is brought into an ON-state, the first transistor for selection is brought into an OFF-state and a reference potential is applied to the first bit line.
In the operation method according to the first constitution of the present invention, preferably, the potential rising of the plate line is performed in a state in which the transistor for selection is in an OFF-state for reading out the data stored in the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line and re-writing the data into the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line, and then the transistor for selection is brought into an ON-state. Further, preferably, after readout of the data stored in the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line, the data are latched in the latch circuits, one (for example, data xe2x80x9c0xe2x80x9d) of binary data is written into these memory cells, then, potential falling of the plate line is performed, and then data (for example, data xe2x80x9c1xe2x80x9d) is re-written into these memory cells.
Alternatively, the operation method according to the first aspect of the present invention may employ a constitution in which
N greater than 2,
latch circuits in the number of N are provided between the first bit line and the second bit line for latching data stored in the first memory cell and the second memory cell, and
re-writing into the first memory cell constituting the n-th-place first sub-memory unit and the second memory cell constituting the n-th-place second sub-memory unit is carried out according to the data latched in the n-th latch circuit.
That is, 1 bit as a complementary data can be stored in the first memory cell constituting the n-th-place first sub-memory unit and the second memory cell constituting the n-th-place second sub-memory unit which memory cells share the plate line (for example, for a pair). The above-constituted operation method according to the first aspect of the present invention will be referred to as xe2x80x9coperation method according to the second constitution of the present inventionxe2x80x9d.
The operation method according to the second constitution of the present invention may employ a constitution in which the m-th-place first memory cell constituting the n-th-place first sub-memory unit and the m-th-place second memory cell constituting the n-th-place second sub-memory unit form a pair to store the complementary data wherein m=1, 2 . . . M.
In the operation method according to the second constitution of the present invention, preferably as well,
the potential rising of the plate line is performed in a state in which the transistor for selection is in an OFF-state for reading out the data stored in the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line and re-writing the data into the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line, and then the transistor for selection is brought into an ON-state. Further, preferably, after readout of the data stored in the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line, the data are latched in the latch circuit, one (for example, data xe2x80x9c0xe2x80x9d) of binary data is written into these memory cells, then, potential falling of the plate line is performed, and then data (for example, data xe2x80x9c1xe2x80x9d) is re-written into these memory cells.
A ferroelectric-type nonvolatile semiconductor memory according to a twelfth aspect of the present invention for achieving the above sixth object comprises a first memory unit and a second memory unit,
the first memory unit comprising;
(A-1) a first bit line,
(B-1) first transistor or transistors for selection in the number of N wherein Nxe2x89xa71,
(C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein Mxe2x89xa72, and
(D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and
the second memory unit comprising;
(A-2) a second bit line,
(B-2) second transistor or transistors for selection in the number of N,
(C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M,
(D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N; the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection; and the second electrode of the m-th-place first memory cell is connected to the common m-th-place plate line wherein m =1, 2 . . . M,
in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are in common in the n-th-place second sub-memory unit; the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection; and the second electrode of the m-th-place second memory cell is connected to the common m-th-place plate line,
and further wherein latch circuits in the number of P are provided between the first bit line and the second bit line for latching data stored in the first memory cell and second memory cell.
In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth aspect of the present invention, there may be employed a constitution in which Nxe2x89xa71 and P=2N are satisfied. The above-constituted ferroelectric-type nonvolatile semiconductor memory will be referred to as ferroelectric-type nonvolatile semiconductor memory according to the twelfth-A aspect of the present invention. In the above constitution, the operation method according to the first constitution of the present invention can be carried out. In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth-A aspect of the present invention, preferably, the (2nxe2x88x921)-th latch circuit latches the data stored in the first memory cell constituting the n-th-place first sub-memory unit, and the 2n-th latch circuit latches the data stored in the second memory cell constituting the n-th-place second sub-memory unit.
The ferroelectric-type nonvolatile semiconductor memory according to the twelfth aspect of the present invention, there may be employed a constitution in which Nxe2x89xa72 and P=N are satisfied. The above-constituted ferroelectric-type nonvolatile semiconductor memory will be referred to as ferroelectric-type nonvolatile semiconductor memory according to the twelfth-B aspect of the present invention. In the above constitution, the operation method according to the second constitution of the present invention can be carried out. In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth-B aspect of the present invention, preferably, the n-th latch circuit latches the data stored in the first memory cell constituting the n-th-place first sub-memory unit and the second memory cell constituting the n-th-place second sub-memory unit.
The operation method of a ferroelectric-type nonvolatile semiconductor memory according to a second aspect of the present invention (to be sometimes referred to as xe2x80x9coperation method according to the second aspect of the present invention) for achieving the above sixth object is an operation method of a ferroelectric-type nonvolatile semiconductor memory comprising;
(A) a bit line,
(B) transistors for selection in the number of N wherein Nxe2x89xa72,
(C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein Mxe2x89xa72, and
(D) plate lines in the number of M,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes are in common in each memory unit,
the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M,
the method comprising performing reading out data stored in the memory cells sharing the plate line in the memory units in the number of N and re-writing data into the memory cells sharing the plate line in the memory units in the number of N by performing potential rising (voltage rising) and potential falling (voltage falling) once each.
The operation method of a ferroelectric-type nonvolatile semiconductor memory according to a third aspect of the present invention (to be sometimes referred to as xe2x80x9coperation method according to the third aspect of the present invention) for achieving the above sixth object is an operation method of a ferroelectric-type nonvolatile semiconductor memory comprising;
(A) a bit line,
(B) transistors for selection in the number of N wherein Nxe2x89xa72,
(C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein Mxe2x89xa72, and
(D) plate lines in the number of M,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes are in common in each memory unit,
the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M,
the method comprising reading out data stored in the memory cells sharing the plate line in the memory units in the number of N by first providing the plate line with a pulse and then consecutively selecting the transistors for selection in the number of N.
In the operation method according to the second or third aspect of the present invention, preferably, the memory units in the number of N are stacked through an insulating interlayer. And, this case can employ the ferroelectric-type nonvolatile semiconductor memory according to the sixth aspect of the present invention including the preferred embodiment thereof.
A ferroelectric-type nonvolatile semiconductor memory according to a thirteenth aspect of the present invention for achieving the above sixth object comprises;
(A) a bit line,
(B) transistors for selection in the number of N wherein Nxe2x89xa72,
(C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein Mxe2x89xa72, and
(D) plate lines in the number of M,
in which
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrodes are in common in each memory unit,
the common first electrode in the n-th memory unit is connected to the bit line through the n-th transistor for selection wherein n=1, 2 . . . N, and
in the n-th memory unit, the second electrode of the m-th memory cell is connected to the m-th plate line common to the memory units wherein m=1, 2 . . . M,
and further in which
latch circuits in the number of at least N are connected to the bit line for latching data stored in the memory cells.
In the ferroelectric-type nonvolatile semiconductor memory according to the thirteenth aspect of the present invention, preferably, the n-th latch circuit latches the data stored in the memory cell constituting the n-th memory unit wherein n=1, 2 . . . N. Further, preferably, the memory units in the number of N are stacked through an insulating interlayer.
The ferroelectric-type nonvolatile semiconductor memory according to any one of the first to sixth aspects of the present invention including the preferred embodiments thereof can be applied to a preferred embodiment of the ferroelectric-type nonvolatile semiconductor memory according to the twelfth or thirteenth aspect of the present invention.
That is, in the ferroelectric-type nonvolatile semiconductor memory according to the twelfth-A aspect of the present invention, for attaining a higher integration, there may be employed a constitution in which a first memory unit constituting a ferroelectric-type nonvolatile semiconductor memory and a first memory unit constituting a ferroelectric-type nonvolatile semiconductor memory adjacent to the above ferroelectric-type nonvolatile semiconductor memory in the extending direction of the first bit line are stacked through an insulating interlayer, and a second memory unit constituting the ferroelectric-type nonvolatile semiconductor memory and a second memory unit constituting the ferroelectric-type nonvolatile semiconductor memory adjacent to the above ferroelectric-type nonvolatile semiconductor memory in the extending direction of the second bit line are stacked through the insulating interlayer.
For attaining a higher integration, for example, the ferroelectric-type nonvolatile semiconductor memory according to the twelfth-B aspect of the present invention may employ a constitution in which the first sub-memory units constituting the first memory unit are stacked through an insulating interlayer and the second sub-memory units constituting the second memory unit are stacked through an insulating interlayer. There may be also employed another constitution in which the first sub-memory unit constituting the first memory unit and the second sub-memory unit constituting the second memory unit are stacked through an insulating interlayer.
Alternatively, the ferroelectric-type nonvolatile semiconductor memory according to any one of the seventh to eleventh aspect of the present invention including the preferred embodiments thereof may be applied to the ferroelectric-type nonvolatile semiconductor memory according to the twelfth or thirteenth aspect of the present invention.
In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth or thirteenth aspect of the present invention or the operation method according to the second or third aspect of the present invention, it is sufficient to satisfy Mxe2x89xa72, and the actual value of M includes, for example, exponents of 2 (2, 4, 8 . . . ). In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth-A aspect of the present invention or the operation method according to the first constitution of the present invention, it is sufficient to satisfy Nxe2x89xa71, and the actual value of N includes, for example, 1 and exponents of 2 (2, 4, 8 . . . ). In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth-B aspect of the present invention or the operation method according to the second constitution of the present invention, it is sufficient to satisfy Nxe2x89xa72, and the actual value of N includes, for example, exponents of 2 (2, 4, 8 . . . ).
In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth or thirteenth aspect of the present invention or the operation method of the ferroelectric-type nonvolatile semiconductor memory, the latch circuit may be constituted of a known latch circuit.
In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth aspect of the present invention or the operation method according to the first aspect of the present invention, a plurality of the first and second memory cells are connected to the first and second transistors for selection in parallel, and the first and second memory cells share the plate line, so that a higher integration of the ferroelectric-type nonvolatile semiconductor memory can be attained. Further, in the operation method according to the first aspect of the present invention, readout of the data stored in the first memory cell and the second memory cell which memory cells share the plate line and re-writing of the data into the first memory cell and the second memory cell which memory cells share the plate line are performed by performing the potential rising and potential falling of the plate line once each, so that the frequency of each memory cell suffering a disturbance can be decreased, and that the rapid operation and low power consumption can be attained. In the ferroelectric-type nonvolatile semiconductor memory according to the twelfth or thirteenth aspect of the present invention, the latch circuit is provided, so that re-writing of the data into the memory cell or re-writing of the data into the first and second memory cells can be reliably performed.
In the operation method according to the second aspect of the present invention, the data stored in the memory cells sharing the plate line in the memory units in the number of N is read out and the data is re-written into the memory cells sharing the plate line in the memory units in the number of N by performing the potential rising and potential falling of the plate line once each, so that the frequency of each memory cell suffering a disturbance can be decreased, and that the rapid operation and low power consumption can be attained. In the operation method according to the third aspect of the present invention, readout of the data stored in the memory cells sharing the plate line in the memory units in the number of N is performed by providing the plate line with a pulse and then consecutively selecting the transistors for selection in the number of N, so that the frequency of each memory cell suffering a disturbance can be decreased, and that the rapid operation and low power consumption can be attained.
The material for constituting the ferroelectric layer in the ferroelectric-type nonvolatile semiconductor memory of the present invention includes bismuth layer compounds, more specifically, a Bi-containing layer perovskite-type ferroelectric material. The Bi-containing layer perovskite-type ferroelectric material comes under so-called non-stoichiometric compounds, and shows tolerance of compositional deviations in both sites of a metal element and anions (O, etc.). Further, it is not a rare case that the above material having a composition deviated from its stoichiometric composition to some extent exhibits optimum electric characteristics. The Bi-containing layer perovskite-type ferroelectric material can be expressed, for example, by the general formula,
(Bi2O2)2+(Amxe2x88x921BmO3m+1)2xe2x88x92
wherein A is one metal selected from the group consisting of metals such as Bi, Pb, Ba, Sr, Ca, Na, K, Cd, etc., and B is one metal selected from the group consisting of Ti, Nb, Ta, W, Mo, Fe, Co and Cr or a combination of a plurality of these metals combined in any amount ratio, and m is an integer of 1 or more.
Alternatively, the material for constituting the ferroelectric layer preferably contains, as a main crystal phase, a crystal phase represented by the formula (1),
(BiX, Sr1xe2x88x92X)2(SrY, Bi1xe2x88x92Y)(TaZ, Nb1xe2x88x92Z)2Odxe2x80x83xe2x80x83(1)
wherein 0.9xe2x89xa6Xxe2x89xa61.0, 0.7xe2x89xa6Yxe2x89xa61.0, 0xe2x89xa6Zxe2x89xa61.0, and 8.7xe2x89xa6dxe2x89xa69.3.
Otherwise, the material for constituting the ferroelectric layer preferably contains, as a main crystal phase, a crystal phase represented by the formula (2),
BiXSrYTa2Odxe2x80x83xe2x80x83(2)
wherein X+Y=3, 0.7xe2x89xa6Yxe2x89xa61.3 and 8.7xe2x89xa6dxe2x89xa69.3.
In the above case, more preferably, the material for constituting the ferroelectric layer preferably contains, as a main crystal phase, at least 85% of a crystal phase represented by the formula (1) or (2). In the above formula (1), (BiX, Sr1xe2x88x92X) means that Sr occupies the site that Bi should have occupied in a crystal structure and that the Bi:Sr amount ratio is X:(1xe2x88x92X). Further, (SrY, Bi1xe2x88x92Y) means that Bi occupies the site that Sr should have occupied in a crystal structure and that the Sr:Bi amount ratio is Y:(1xe2x88x92Y). The material for constituting the ferroelectric layer and containing, as a main crystal phase, the crystal phase of the above formula (1) or (2), may contain an oxide of Bi, oxides of Ta and Nb and composite oxides of Bi, Ta and Nb to some extent.
Alternatively, the material for constituting the ferroelectric layer may contain a crystal phase represented by the formula (3),
BiX(Sr, Ca, Ba)Y(TaZ, Nb1xe2x88x92Z)2Odxe2x80x83xe2x80x83(3)
wherein 1.7xe2x89xa6Xxe2x89xa62.5, 0.6xe2x89xa6Yxe2x89xa61.2, 0xe2x89xa6Zxe2x89xa61.0 and 8.0xe2x89xa6dxe2x89xa610.0.
(Sr, Ca, Ba) stands for one element selected from the group consisting of Sr, Ca and Ba. When the above material for the ferroelectric layer, having the above formulae, is expressed by a stoichiometric composition, the composition includes Bi2SrTa2O9, Bi2SrNb2O9, Bi2BaTa2O9 and Bi2SrTaNbO9. Otherwise, the material for constituting the ferroelectric layer also includes Bi4SrTi4O15, Bi4Ti3O12 and Bi2PbTa2O9. In these cases, the amount ratio of the metal elements may be varied to such an extent that the crystal structure does not change. That is, the above material may have a composition deviated from its stoichiometric composition in both sites of metal elements and oxygen element.
Further, the material for constituting the ferroelectric layer includes PbTiO3, lead titanate zirconate [PZT, Pb(Zr1xe2x88x92y, Tiy)O3 wherein 0 less than y less than 1] which is a solid solution of PbZrO3 and PbTiO3 having a perovskite structure, and PZT-containing compounds such as PLZT which is a metal oxide prepared by adding La to PZT and PNZT which is a metal oxide prepared by adding Nb to PZT.
In the above materials for constituting the ferroelectric layer, the crystallization temperature can be changed by deviating their compositions from their stoichiometric compositions.
In the ferroelectric-type nonvolatile semiconductor memory according to the sixth aspect or in a preferred embodiment of the ferroelectric-type nonvolatile semiconductor memory according to any one of the first to fifth and seventh to thirteenth aspects of the present invention, the above materials for constituting the ferroelectric layers are properly selected, whereby it can be attained that the ferroelectric layer constituting the memory cells positioned above has a lower crystallization temperature than the ferroelectric layer constituting the memory cells positioned below, or that the ferroelectric layer of the memory cells constituting the memory unit or the sub-memory unit positioned above has a lower crystallization temperature than the ferroelectric layer of the memory cells constituting the memory unit or the sub-memory unit positioned below. The following Table 1 shows crystallization temperatures of typical materials for constituting the ferroelectric layers, while the materials for constituting the ferroelectric layers shall not be limited thereto.
In the ferroelectric-type nonvolatile semiconductor memories according to various aspects of the present invention, there may be employed a constitution in which the first electrode is formed below the ferroelectric layer and the second electrode is formed on the ferroelectric layer (that is, the first electrode corresponds to the lower electrode and the second electrode corresponds to the upper electrode), or there may be employed a constitution in which the first electrode is formed on the ferroelectric layer and the second electrode is formed below the ferroelectric layer (that is, the first electrode corresponds to the upper electrode and the second electrode corresponds to the lower electrode). There may be employed a constitution in which the plate line extends from the second electrode, or the plate line is formed separately from the second electrode and is connected to the second electrode. In the latter case, the wiring material for constituting the plate line includes, for example, aluminum and an aluminum-containing alloy. The structure in which the first electrode is common specifically includes a structure in which the first electrode in the form of a stripe is formed and the ferroelectric layer is formed on the entire surface of the first electrode in the form of a stripe. In the above structure, an overlapping region of the first electrode, the ferroelectric layer and the second electrode corresponds to a memory cell or a capacitor member. In addition, the structure in which the first electrode is common includes a structure in which ferroelectric layers are formed on predetermined regions of the first electrode and the second electrodes are formed on the ferroelectric layers, and a structure in which the first electrodes are formed in predetermined surface regions of a wiring layer, the ferroelectric layers are formed on the first electrodes and the second electrodes are formed on the ferroelectric layers, although the above structure shall not be limited thereto.
For forming the ferroelectric layer, a ferroelectric thin film is formed, and a step to come thereafter, the ferroelectric thin film is patterned. Some cases require no patterning of the ferroelectric thin film. The ferroelectric thin film can be formed by a method suitable for a material that is to constitute the ferroelectric thin film, such as an MOCVD method, a pulse laser abrasion method, a sputtering method or a sol-gel method. Further, the ferroelectric thin film can be patterned, for example, by an anisotropic ion etching (RIE) method.
In the present invention, the material for constituting the first electrode and second electrode include, for example, Ir, IrO2xe2x88x92X, SrIrO3, Ru, RuO2xe2x88x92X, SrRuO3, Pt, Pt/IrO2xe2x88x92X, Pt/RuO2xe2x88x92X, Pd, a Pt/Ti stacked structure, a Pt/Ta stacked structure, a Pt/Ti/Ta stacked structure, La0.5Sr0.5CoO3(LSCO), a Pt/LSCO stacked structure and YBa2Cu3O7. The value of the above X is in the range of 0xe2x89xa6X less than 2. In the above stacked structures, a material described before xe2x80x9c/xe2x80x9d constitutes the upper layer, and a material described after xe2x80x9c/xe2x80x9d constitutes the lower layer. The first electrode and the second electrode may be constituted of one material, materials of the same kind or materials of different kinds. For forming the first electrode or the second electrode, a first electrode material layer or a second electrode material layer is formed, and in a step to come thereafter, the first electrode material layer or the second electrode material layer is patterned. The first electrode material layer or the second electrode material layer can be formed by a method properly suitable for the materials for constituting the first electrode material layer or the second electrode material layer, such as a sputtering method, a reactive sputtering method, an electron beam deposition method, an MOCVD method or a pulse laser abrasion method. The first electrode material layer or the second electrode material layer can be patterned, for example, by an ion milling method or an RIE method.
In the present invention, the material for constituting the insulating interlayer includes silicon oxide (SiO2), silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG and LTO.
The transistor for selection (transistor for switching) and various transistors can be constituted, for example, of known MIS type FETs or MOS type FETs. The material for constituting the bit line includes an impurity-doped polysilicon and a refractory metal material. The common first electrode and the transistor for selection can be electrically connected through a contact hole made in an insulation layer formed between the common first electrode and the transistor for selection or through a contact hole made in the above insulation layer and a wiring layer formed on the insulation layer. The material for constituting the insulation layer includes silicon oxide (SiO2), silicon nitride (SiN), SION, SOG, NSG, BPSG, PSG, BSG and LTO.